This invention relates to voltage pulse amplifiers and, in particular, to an amplifier which is well-suited to serve as a TTL-to-MOS level shifter.
Many of today's computer logic circuits are of the junction transistor TTL configuration while many of the random access memory arrays are fabricated with MOS transistors. There is an obvious need for level shifter amplifiers to convert TTL voltage logic levels to MOS voltage logic levels. One commercially available TTL-to-MOS level shifter utilizes a totem pole output stage which consists of a pull-up and a saturation pull-down junction transistor. One of the problems with this type of configuration is that minority carrier storage which occurs when the pull-down transistor is operated in saturation causes both transistors to conduct simultaneously during switching. This provides a direct path between the power supply utilized and ground potential which results in undesirable relatively large current spikes in the output stage.
Various suggestions have been made to alleviate output current spiking in the above configuration. The inclusion of a series resistance in the collector of the pull-up transistor does not eliminate the problem but merely limits its severity. In the application of a MOS level shifter where high capacitive loads and relatively large voltage swings are involved, a series resistor significantly degrades response time. Another solution is the use of a Schottky barrier clamp diode across the collector base junction of the pull-down transistor. This solution is likewise undesirable since it adds significant capacitive loading which also significantly degrades response time. An economically viable solution to this problem requires the addition of few circuit elements which do not require much silicon area for implementation and do not significantly increase circuit power dissipation or degrade response time.